# Byte-Wise CRC Calculations

@article{Perez1983ByteWiseCC, title={Byte-Wise CRC Calculations}, author={Aram Aquilino Morales Perez}, journal={IEEE Micro}, year={1983}, volume={3}, pages={40-50} }

A cyclic redundancy code can be calculated on bytes instead of bits. One byte-oriented method reduces calculation time by a factor of almost four.

#### 87 Citations

"On the Fly" CRC-16 Byte-wise Calculation for 8088-based Computers

- Computer Science
- IEEE Micro
- 1985

A cyclic redundancy code, or CRC, is often used to ensure the integrity of messages in data communications and is faster than its bit-wise counterpart. Expand

A tutorial on CRC computations

- Computer Science
- IEEE Micro
- 1988

The theory of cyclic redundancy codes (CRS) is reviewed. Four software algorithms for performing CRC computations are described: table lookup, reduced table lookup, on-the-fly, and wordwise. They are… Expand

Automatic generation of parallel CRC circuits

- Computer Science
- IEEE Design & Test of Computers
- 2001

A generic VHDL description of parallel CRC circuits lets designers synthesize CRC circuits for any generator polynomial or required amount of parallelism. Expand

A method for updating a cyclic redundancy code

- Computer Science
- IEEE Trans. Commun.
- 1992

A method is described for updating the check bits of a cyclic redundancy check (CRC) code, based on knowledge of the altered bits and their position in the frame, which is independent of the frame size. Expand

Parallel CRC generation

- Computer Science
- IEEE Micro
- 1990

A method of designing hardware parallel encoders for CRCs that is based on digital system theory and z-transforms is presented, which allows designers to derive the logic equations of the parallel encoder circuit for any generator polynomial. Expand

CRC generation for protocol processing

- Computer Science
- 2000

In order to provide error detection in communication networks a method called Cyclic Redundancy Check has been used for almost 40 years. This algorithm is widely used in computer networks of today ...

Word-parallel CRC computation on VLIW DSP

- Computer Science
- 2002

A method is proposed for using the toll power of a very long instruction word (VLIW) digital signal processor (DSP) architecture in CRC computation to at least four times faster for 8, 16 and 32 bits CRC. Expand

Some transforms in cyclic redundancy check (CRC) computation

- Computer Science
- 2011 International Conference on Electrical and Control Engineering
- 2011

Some transforms in cyclic redundancy check (CRC) computation, such as the multiplication of two messages' polynomials, shift, complement, and different initial (defaulted) remainder of a message, are studied and find that these transforms are useful in CRC computation implementations of both software and hardware. Expand

A new parallel algorithm for CRC generation

- Computer Science
- 2000 IEEE International Conference on Communications. ICC 2000. Global Convergence Through Communications. Conference Record
- 2000

A new parallel algorithm for CRC generation and its software as well as hardware implementation is described, which yields an unlimited speed-up potential over the bit-wise serial algorithm. Expand

A high-performance CMOS 32-bit parallel CRC engine

- Computer Science
- 1999

Design highlights for a 32-bit parallel cyclic redundancy check (CRC) generator engine are presented and a compact layout is achieved by predecoding eight groups of four bits followed by performing a binary tree reduction on nets that are sorted by fanout. Expand